【LTspice入門】LTspiceでマイコンのPWM波形発生モデルを作成・シミュレートする方法

            $ tree -L 3
.
└ LTspiceXVII
  └─ lib
      ├─ sub
      │   └─ pwm-test
      │      └── pwm1.subckt
      └─ sym
          └─ pwm-test
              └── pwm1.asy
        

            Version 4
SymbolType CELL
LINE Normal -20 -128 -20 -112
LINE Normal 20 -128 20 -112
LINE Normal -8 -100 8 -100
RECTANGLE Normal -112 -128 112 128
ARC Normal -20 -124 4 -100 -20 -112 -8 -100
ARC Normal -4 -124 20 -100 8 -100 20 -112
WINDOW 0 0 -144 Center 2
WINDOW 3 -1 151 Center 2
SYMATTR Prefix X
SYMATTR Value MY_PWM_TEST
SYMATTR ModelFile pwm-test/pwm1.subckt
SYMATTR Description Generic MicroController for PWM wave generator.
PIN -112 -96 LEFT 8
PINATTR PinName VCC
PINATTR SpiceOrder 1
PIN -112 -32 LEFT 8
PINATTR PinName 2
PINATTR SpiceOrder 2
PIN -112 32 LEFT 8
PINATTR PinName 3
PINATTR SpiceOrder 3
PIN -112 96 LEFT 8
PINATTR PinName PWM
PINATTR SpiceOrder 4
PIN 112 96 RIGHT 8
PINATTR PinName 5
PINATTR SpiceOrder 5
PIN 112 32 RIGHT 8
PINATTR PinName 6
PINATTR SpiceOrder 6
PIN 112 -32 RIGHT 8
PINATTR PinName 7
PINATTR SpiceOrder 7
PIN 112 -96 RIGHT 8
PINATTR PinName GND
PINATTR SpiceOrder 8
        

            VCC (1)
PWM (4)
GND (8)
        

            ** Pin Assignment Ordering
* VCC (1)
* PWM (4)
* GND (8)
.SUBCKT MY_PWM_TEST 1 2 3 4 5 6 7 8
** Parameters for PWM shape
* .params freq=500
* .params duty=0.3
B1 4 8 V=V(1) * if(time*freq - int(time*freq) + 0.5 - duty, 0, 1)
.ENDS
        

            .param freq=750
.param duty=0.3
.tran 10m
        

            .SUBCKT Opamp_AVR_DB 1 2 3 4 5
*#ASSOC Category="Microcontroller Peripherals" symbol=opamp
*                     | | | | |
*                     | | | | Output
*                     | | | Negative Supply
*                     | | Positive Supply
*                     | Inverting Input
*                     Non-inverting Input
*
*
********************************************************************************
* Software License Agreement                                                   *
*                                                                              *
* The software supplied herewith by Microchip Technology Incorporated (the     *
* 'Company') is intended and supplied to you, the Company's customer, for use  *
* soley and exclusively on Microchip products.                                 *
*                                                                              *
* The software is owned by the Company and/or its supplier, and is protected   *
* under applicable copyright laws. All rights are reserved. Any use in         *
* violation of the foregoing restrictions may subject the user to criminal     *
* sanctions under applicable laws, as well as to civil liability for the       *
* breach of the terms and conditions of this license.                          *
*                                                                              *
* THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES, WHETHER    *
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED        *
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO  *
* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR    *
* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.     *
********************************************************************************
*
* The following op-amps are covered by this model:
*      Opamp_AVR_DB,Opamp_PIC18_Q14,Opamp_PIC18_Q71
*
* Date of model creation: 9-8-2020_2:02:25_PM
* Level of Model Creator: 1P02 / 08-31-20
*
* Revision History:
*      V1.0 - Initial Release - RW - 07/01/20
*      V1.1 - Release - RW - 09/01/20
*      V1.2 - Updates - RW - 09/08/20 
*       
*       
*
* Recommendations:
*      Use PSPICE (or SPICE 2G6; other simulators may require translation)
*      For a quick, effective design, use a combination of: data sheet
*            specs, bench testing, and simulations with this macromodel
*      For high impedance circuits, set GMIN=100F in the .OPTIONS statement
*
* Supported:
*      Typical performance for temperature range (-40 to 125) degrees Celsius
*      DC, AC, Transient, and Noise analyses.
*      Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
*            open loop gain, voltage ranges, supply current, ... , etc.
*      Temperature effects for Ibias, Iquiescent, Iout short circuit 
*            current, Vsat on both rails, Slew Rate vs. Temp and P.S.
*
* Not Supported:
*      Some Variation in specs vs. Power Supply Voltage
*      Vos distribution, Ib distribution for Monte Carlo
*      Distortion (detailed non-linear behavior)
*      Some Temperature analysis
*      Process variation
*      Behavior outside normal operating region
*
* Known Discrepancies in Model vs. Datasheet:
*
*?@ Start SIMPLIS Encryption $$WC_SIMPLIS_ENCRYPT_TAG$$
*       
*
* Input Stage 
*
C2  1 4 5.00P
C3  2 4 5.00P
R19  1 4 100E12
R20  2 4 100E12
R21  1 2 100E12
C13  1 2 3.00P
V10  3 10 -500M
R10 10 11 69.0K
R11 10 12 69.0K
G10 10 11 10 11 1.44M
G11 10 12 10 12 1.44M
M12 11 14 15 15 NMI 
M14 12 2 15 15 NMI 
I15 15 4 500U
V16 16 4 -300M
GD16 16 1 TABLE { V(16,1) } ((-100,-10.0E-18)(0,0)(1m,1u)(2m,1m)) 
V13 3 13 -300M
GD13 2 13 TABLE { V(2,13) } ((-100,-10.0E-18)(0,0)(1m,1u)(2m,1m)) 
*
* Noise Stage 
*
I20 21 20 1.00
D20 20  0 DN1
D21  0 21 DN1
I22 22 23 1N
R22 22 0  1k
R23  0 23 1k
E12 71 14 VALUE { (0.00) + V(20) * 174M + V(21) * 174M + V(22) * 174M + V(23) * 174M }
I73 0 70 DC 1
R74 0 70 1 TC=30.0U
E75 1 71 VALUE {V(70)-1}
EG1 VIBIASP 0 62 0 1u
GB1 1 0 VIBIASP 0 1
EG2 VIBIASM 0 622 0 1u
GB2 2 0 VIBIASM 0 1
I61 0 62 DC 1uA
VA200 62A 62 DC 0.00
R62 0 62A REXP  5K
I622 0 622 DC 1uA
VA201 622A 622 DC 0.00
R62A 0 622A REXPM  5K
R61 0 61 1 TC=1.50M,-1.76U
G61 3 4 61 0 1
G60 0 61 TABLE { V(3, 4) } ((0, 0)(1.00,920E-18)(1.6,840U)(1.75,858U)(2.00,885U)(2.2,920U)(5.5,980U))
*
* PSRR / CMRR 
*
G57  0 57 VALUE { V(35) * 5.00M + V(118) + V(128) + V(137) } 
G110 0 110 3 0 28.1U
R110 110 0 1G 
GR110 110 0 110 0 1m 
C110 110 0 534N
G111 0 111 110 0 1 
L111 111 112 53.0U
R112 112 0 1G 
GR112 112 0 112 0 1 
G114 0 114 111 0 1 
R114 114 0 1G 
C114 114 0 5.30N
GR114 114 0 114 0 1 
G115 0 115 114 0 1 
L115 115 116 159P
R116 116 0 1G 
GR116 116 0 116 0 1 
G117 0 117 115 0 1 
R117 117 0 1G 
C117 117 0 5.30N
GR117 117 0 117 0 1 
G118 0 118 117 0 1 
L118 118 119 159P
R119 119 0 1G 
GR119 119 0 119 0 1 
G120 0 120 4 0 28.1U
R120 120 0 1G 
GR120 120 0 120 0 1m 
C120 120 0 534N
G121 0 121 120 0 1 
L121 121 122 35.3U
R122 122 0 1G 
GR122 122 0 122 0 1 
G124 0 124 121 0 1 
R124 124 0 1G 
C124 124 0 5.30N
GR124 124 0 124 0 1 
G125 0 125 124 0 1 
L125 125 126 159P
R126 126 0 1G 
GR126 126 0 126 0 1 
G127 0 127 125 0 1 
R127 127 0 1G 
C127 127 0 5.30N
GR127 127 0 127 0 1 
G128 0 128 127 0 1 
L128 128 129 159P
R129 129 0 1G 
GR129 129 0 129 0 1 
G130 0 130 VALUE { ( V(15) ) * 28.1U}
R130 130 0 1G 
GR130 130 0 130 0 1m 
C130 130 0 534N
G131 0 131 130 0 1 
L131 131 132 31.8U
R132 132 0 1G 
GR132 132 0 132 0 1 
G133 0 133 131 0 1 
R133 133 0 1G 
C133 133 0  530N
GR133 133 0 133 0 1 
G134 0 134 133 0 1 
L134 134 135 159P
R135 135 0 1G 
GR135 135 0 135 0 1 
G137 0 137 134 0 1 
R137 137 0 1G 
C137 137 0  159P
GR137 137 0 137 0 1 
*
* OP Amp Output Gain / Response 
*
G30 0 30 TABLE { V(12, 11) } ((-5.5,-16.5)(-0.005,-0.005)(0,0)(0.005,0.005)(5.5,16.5))
R30 30  0 1.00K
G31 0 31 3 4 24.9
I31 0 31 DC 208
R31 31 0 1
E_VDDMAX VDE 0 3 4 1
V_VDD1 31VDD1 0 1.8
V_VDD2 31VDD2 0 5.5
G_ABMII2 0 31B VALUE { V(31)*(LIMIT(((V(31VDD1)-V(VDE))/(V(31VDD1)-V(31VDD2))), 0, 1))}
R_R3 31A 0 1 TC=2.87M, -4.71U
G_ABMII1 0 31A VALUE { V(31)*(LIMIT(((V(VDE)-V(31VDD2))/(V(31VDD1)-V(31VDD2))), 0, 1))}
G_G6 30 31C TABLE { V(30, 31C) } ((-100,-1n)(0,0)(1m,0.1)(101m,190.1))
E_ABM1 31C 0 VALUE { (V(31A) + V(31B)) }
R_R8 31B 0 1 TC=2.18M, -3.59U
G32 32 0 3 4 33.0
I32 32 0 DC 286
R32 32  0 1 
G_ABMII22 32B 0 VALUE { V(32)*(LIMIT(((V(31VDD1)-V(VDE))/(V(31VDD1)-V(31VDD2))), 0, 1))}
R_R23 32A 0 1 TC=1.76M, -6.81U
G_ABMII21 32A 0 VALUE { V(32)*(LIMIT(((V(VDE)-V(31VDD2))/(V(31VDD1)-V(31VDD2))), 0, 1))}
G_G26 32C 30 TABLE { V(30, 32C) } ((-101m,190.1)(-1m,0.1)(0,0)(100,-1n))
E_ABM21 0 32C VALUE { (V(32A) + V(32B)) }
R_R28 32B 0 1 TC=1.24M, -6.78U
G6  0 33 30 0 1m
R6  33 0 1K
G34  0 34 33 0 17.7M
R34  34 0 1K
C34  34 0 534N
G37  0 37 34 0 1m
R37  37 0 1K
C37  37 0 5.30P
G37A 0 37A 37 0 1m
R37A 37A 0 1G
GR37A 37A 0 37A 0 1m
C37A  37A 0 5.30P
G377A 0 377A 37A 0 1m
R377A 377A 0 1G
GR377A 377A 0 377A 0 1m
C377A  377A 0 795E-15
G378A 0 378A 377A 0 1m
R378A 378A 0 1G
GR378A 378A 0 378A 0 1m
C378A  378A 0 795E-15
G38  0 38 378A 0 1m
RR38  39 0 1K
L38  38 39 17.6U
E38  35 0 38 0 1
G35 33 0 TABLE { V(35,3) } ((-1,-1p)(0,0)(40.0,1n))(44.0,1))
G36 33 0 TABLE { V(35,4) } ((-44.0,-1)((-40.0,-1n)(0,0)(1,1p))
*
* Output Impedance / Saturation / Current Limit 
*
R80 50 0 100MEG
VR57 57 96 0
R57X 57 96 1G
F1 0 50 VR57 1
R57 57  0 200
GD55 55 57 TABLE { V(55,57) } ((-0.2m,-250)(-0.1m,-1m)(0,0)(10,1p))
GD56 57 56 TABLE { V(57,56) } ((-0.2m,-250)(-0.1m,-1m)(0,0)(10,1p))
E55 55  0 VALUE { -15.0M + V(3) * 1 + V(51) * -33.0M }
E56 56  0 VALUE { 17.0M + V(4) * 1 + V(52) * -38.4M }
R51 51 0 1k
R52 52 0 1k
GD51 50 51 TABLE { V(50,51) } ((-10,-1n)(0,0)(1m,1m)(2m,1))
GD52 50 52 TABLE { V(50,52) } ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
G51  3  0 VALUE { -500U + V(51) * 1M }
G52  0  4 VALUE { -500U + V(52) * -1M }
GD24A 98 98A TABLE { V(98,98A) } ((-3m,-1000)(-2m,-10)(-1m,-1)(0,0)(1,1n))
GD24B 98 98B TABLE { V(98,98B) } ((-1,-1n)(0,0)(1m,1)(2m,10)(3m,1000))
R24A 0 98A 1 TC=-3.10M,5.01U
R24B 0 98B 1 TC=-1.57M,-2.87U
G71 96 5 99 0 1
G70 0 98 TABLE { V(96,5) } ((-11.0,-7.8M)(-1.00M,-7.72M)(0,0)(1.00M,9.31M)(11.0,9.41M))
E99 99 0 VALUE { V(98) * LIMIT((( V(3) - V(4) ) * 2.39 + -3.30), 0.00, 1E6 ) * LIMIT((( V(3) - V(4) ) * 1.25 + -1.25), 0, 1) }
D3 4 5 DESD
D4 5 3 DESD
* Models
.MODEL NMI NMOS(L=2.00U W=42.0U KP=200U LEVEL=1 )
.MODEL DESD  D   N=1 IS=1.00E-15
.MODEL DN1 D   IS=1P KF=9.5U AF=1
.MODEL REXP  RES TCE=0.00
.MODEL REXPM  RES TCE=0.00
*
*
*
*?@ End SIMPLIS Encryption
*
.ENDS  Opamp_AVR_DB
        

            .SUBCKT Opamp_AVR_DB 1 2 3 4 5
*                     | | | | |
*                     | | | | Output
*                     | | | Negative Supply
*                     | | Positive Supply
*                     | Inverting Input
*                     Non-inverting Input